pmosfet的偏温退化:机理与抑制

M. Makabe, T. Kubota, T. Kitano
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引用次数: 33

摘要

我们利用载流子分离分析研究了pMOSFET的偏置-温度(BT)降解。发现电子从栅电极隧穿到衬底会在SiO/sub /Si界面处引起冲击电离,并导致捕获电荷和界面态的产生。在SiO/ sub2 /膜中掺入高浓度的硼可以抑制BT的降解。这被认为是隧穿电子电流抑制的结果。由于BT的降解也可以通过减少栅电极和漏极之间的氧化物中的电场来抑制。换句话说,BT降解在on状态下比off状态下更低。通过改变侧壁形成工艺,也可以减小栅极与漏极之间的电场。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Bias-temperature degradation of pMOSFETs: mechanism and suppression
We investigated pMOSFET Bias-Temperature (BT) degradation by using carrier separation analysis. Electrons tunneling from gate electrode to substrate were found to cause impact ionization at the SiO/sub 2//Si interface and result in the creation of trapped charges and interface states. A higher-concentration boron incorporation into the SiO/sub 2/ film was found to suppress BT degradation. This is considered to be a result of tunneling electron current suppression. Degradation due to BT can also be suppressed by reducing the electric field in the oxide between the gate electrode and drain. In other words, BT degradation is lower for the ON-state than the OFF-state. The electric field between the gate electrode and drain can also be reduced by changing the side wall formation process.
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