一种用于超高电流应用的48v - 1v开关母线转换器

IF 1 4区 工程技术 Q4 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS
Yicheng Zhu, Ting Ge, N. Ellis, Jiarui Zou, R. Pilawa-Podgurski
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引用次数: 1

摘要

本文介绍了一种用于下一代超高功率数字负载(如cpu、gpu、asic等)的48v到1v直接功率转换的超高电流开关总线转换器。在提出的拓扑结构中,两个2对1的交换电容(SC)前端通过两条交换总线与四个10支路的串联电容降压(SCB)模块合并。与基于直流母线的架构相比,基于开关母线的架构不需要直流母线电容,减少了开关的数量,保证了完全的软充电操作。通过每个SCB模块内的两相操作,开关母线转换器扩展了最大占空比,并实现了20比1的非常大的SC级转换比。与现有的48v到1v混合SC演示相比,所提出的拓扑结构具有最低的归一化开关应力和最小的归一化无源元件体积,与先前的解决方案相比,具有更高的效率和更高的功率密度的潜力。采用定制的四相耦合电感器和栅极驱动子板,设计并构建了48v到1v的硬件原型。针对SCB模块的高侧开关,设计了由门驱动电荷泵电路和级联自举电路组成的混合门驱动电路,克服了传统级联自举电路的电压累积降问题。硬件样机在1200 a的输出电流下进行了测试,达到了92.4%的峰值系统效率、87.5%的满载效率(包括栅极驱动损耗)和607 W/in3的功率密度(按箱体体积计算)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 48-V-to-1-V Switching Bus Converter for Ultra-High-Current Applications
This paper presents an ultra-high-current switching bus converter with direct 48-V-to-1-V power conversion for next-generation ultra-high-power digital loads (e.g., CPUs, GPUs, ASICs, etc.). In the proposed topology, two 2-to-1 switched-capacitor (SC) front-ends are merged with four 10-branch series-capacitor buck (SCB) modules through two switching buses. Compared to the DC-bus-based architecture, the switching-bus-based architecture does not require DC bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. Through two-phase operation within each SCB module, the switching bus converter extends the maximum duty ratio and achieves a very large SC stage conversion ratio of 20-to-1. Compared to existing 48-V-to-1-V hybrid SC demonstrations, the proposed topology has the lowest normalized switch stress and the smallest normalized passive component volume, showing great potential for both higher efficiency and higher power density than prior solutions. A 48-V-to-1-V hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards. Hybrid gate drive circuitry comprising gate-driven charge pump circuits and cascaded bootstrap circuits was customized for the high-side switches in the SCB modules to overcome the challenge of accumulative voltage drops in the conventional cascaded bootstrap circuit. The hardware prototype was tested up to 1200-A output current and achieved 92.4% peak system efficiency, 87.5% full-load efficiency (including gate drive loss), and 607 W/in3 power density (by box volume).
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来源期刊
CiteScore
1.60
自引率
0.00%
发文量
124
审稿时长
4.2 months
期刊介绍: COMPEL exists for the discussion and dissemination of computational and analytical methods in electrical and electronic engineering. The main emphasis of papers should be on methods and new techniques, or the application of existing techniques in a novel way. Whilst papers with immediate application to particular engineering problems are welcome, so too are papers that form a basis for further development in the area of study. A double-blind review process ensures the content''s validity and relevance.
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