嵌入式Si扇出:一种低成本晶圆级封装技术,无需成型和脱粘工艺

Daquan Yu, Zhe-Yu Huang, Zhiyi Xiao, Li Yang, Min Xiang
{"title":"嵌入式Si扇出:一种低成本晶圆级封装技术,无需成型和脱粘工艺","authors":"Daquan Yu, Zhe-Yu Huang, Zhiyi Xiao, Li Yang, Min Xiang","doi":"10.1109/ECTC.2017.166","DOIUrl":null,"url":null,"abstract":"Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out wafer level packaging (FOWLP) aroused more interests and showed the advantages of higher number of I/Os, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOWLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage wafer handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SiP, advanced FOWLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required. In this paper, the development of a wafer level embedded silicon fan-out, named eSiFO technology was reported. For eSiFO package, the known good dies are embedded in the cavities formed on silicon wafer and the micro-scale gap between the dies and cavities is filled by epoxy material. An almost entire silicon surface was constructed as the fan-out area for RDL and BGA. The process is simple comparing with standard FOWLP since there is no molding, temporary bonding and de-bonding process. The key advantage is that the CTE for dies and silicon wafer is same and there is no warpage issue during manufacturing which results in good packaging yield. An eSiFO package with size of 3.3×3.3mm, one layer RDL and 50 BGAs was successfully demonstrated. The results proved that the process of eSiFO was simple and suitable for high density system integration with ultra low profile. Various reliability tests were carried out to study the package reliability and no failure was found. The simulation results show that for the same package, eSiFO has lower thermal stress than FOWLP using EMC.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"90 1","pages":"28-34"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology without Molding and De-Bonding Processes\",\"authors\":\"Daquan Yu, Zhe-Yu Huang, Zhiyi Xiao, Li Yang, Min Xiang\",\"doi\":\"10.1109/ECTC.2017.166\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out wafer level packaging (FOWLP) aroused more interests and showed the advantages of higher number of I/Os, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOWLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage wafer handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SiP, advanced FOWLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required. In this paper, the development of a wafer level embedded silicon fan-out, named eSiFO technology was reported. For eSiFO package, the known good dies are embedded in the cavities formed on silicon wafer and the micro-scale gap between the dies and cavities is filled by epoxy material. An almost entire silicon surface was constructed as the fan-out area for RDL and BGA. The process is simple comparing with standard FOWLP since there is no molding, temporary bonding and de-bonding process. The key advantage is that the CTE for dies and silicon wafer is same and there is no warpage issue during manufacturing which results in good packaging yield. An eSiFO package with size of 3.3×3.3mm, one layer RDL and 50 BGAs was successfully demonstrated. The results proved that the process of eSiFO was simple and suitable for high density system integration with ultra low profile. Various reliability tests were carried out to study the package reliability and no failure was found. The simulation results show that for the same package, eSiFO has lower thermal stress than FOWLP using EMC.\",\"PeriodicalId\":6557,\"journal\":{\"name\":\"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"90 1\",\"pages\":\"28-34\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2017.166\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2017.166","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 27

摘要

先进封装技术在器件小型化、系统集成化、性能提升等方面发挥着越来越重要的作用。在众多新的封装技术中,扇出式晶圆级封装(FOWLP)引起了更多的关注,并因消除了衬底而显示出更高的I/ o数量、集成灵活性、低成本和小尺寸等优势。然而,使用环氧模化合物(EMC)材料的FOWLP面临着许多技术挑战,例如晶圆翘曲处理,难以制造细间距再分布层(RDL),以及由于芯片与EMC之间的CTE不匹配而导致的大型封装可靠性问题。此外,对于高性能SiP,需要具有多层细间距rdl的先进FOWLP,出色的对准精度,模具之间最短的互连路由和超小的外形尺寸。本文报道了一种晶圆级嵌入式硅扇出(eSiFO)技术的发展。对于eSiFO封装,将已知好的模具嵌入硅片上形成的空腔中,并用环氧树脂材料填充模具与空腔之间的微尺度间隙。构建了几乎整个硅表面作为RDL和BGA的扇形区域。与标准FOWLP相比,该工艺简单,没有成型,临时粘接和脱粘过程。关键的优点是,CTE的模具和硅片是相同的,没有翘曲问题,在制造过程中,导致良好的封装良率。成功地演示了一个尺寸为3.3×3.3mm、一层RDL和50个BGAs的eSiFO封装。结果表明,eSiFO工艺简单,适合超低轮廓高密度系统集成。进行了各种可靠性试验,研究了包装的可靠性,未发现任何故障。仿真结果表明,在相同的封装条件下,eSiFO比采用电磁兼容的FOWLP具有更低的热应力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology without Molding and De-Bonding Processes
Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out wafer level packaging (FOWLP) aroused more interests and showed the advantages of higher number of I/Os, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOWLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage wafer handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SiP, advanced FOWLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required. In this paper, the development of a wafer level embedded silicon fan-out, named eSiFO technology was reported. For eSiFO package, the known good dies are embedded in the cavities formed on silicon wafer and the micro-scale gap between the dies and cavities is filled by epoxy material. An almost entire silicon surface was constructed as the fan-out area for RDL and BGA. The process is simple comparing with standard FOWLP since there is no molding, temporary bonding and de-bonding process. The key advantage is that the CTE for dies and silicon wafer is same and there is no warpage issue during manufacturing which results in good packaging yield. An eSiFO package with size of 3.3×3.3mm, one layer RDL and 50 BGAs was successfully demonstrated. The results proved that the process of eSiFO was simple and suitable for high density system integration with ultra low profile. Various reliability tests were carried out to study the package reliability and no failure was found. The simulation results show that for the same package, eSiFO has lower thermal stress than FOWLP using EMC.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信