基于非电阻度量的25纳米多电平PCRAM读取方案

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI:10.1109/CICC.2015.7338358

Junho Cheon, Insoo Lee, Changyong Ahn, M. Stanisavljevic, A. Athmanathan, N. Papandreou, H. Pozidis, E. Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong Kang, J. Chun

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引用次数: 10

摘要

介绍了一种高密度多级PCRAM的无电阻读出方案。增强了具有漂移弹性的非电阻读度量，使其适用于具有较大寄生时间常数的高密度存储阵列。采用25nm技术的1G PCM单元以具有分层位线方案的单个16G单元芯片的形式结构。此外，每组内置32个6位SAR-ADC实例，具有用于自适应数据检测的特定逻辑作为感测放大器。实验结果表明，在2Gb多层级密度的数据库中，包含字行定位和自适应数据检测方案，总读取延迟为450ns。

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Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology

A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line scheme. Furthermore, 32 instances of 6bit SAR-ADC per bank are built-in with specific logic for adaptive data detection as a sense-amplifier. Experimental results for a bank of 2Gb multi-level density are demonstrated with total read latency of 450ns including word-line settling and the adaptive data detection scheme.

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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