用于2.4 GHz孔径接收机的实时二维FIR梯形数字滤波器

V. Ariyarathna, V. A. Coutinho, S. Pulipati, A. Madanayake, Ravi T. Wijesekara, C. Edussooriya, Len T. Bruton§, T. Gunaratne, R. Cintra
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引用次数: 3

摘要

提出了一种基于二维有限脉冲响应(FIR)梯形滤波器的波束形成阵列接收机的实现方法。设计了一种2.4 GHz 16元接收模IQ阵列,用于物理测量二维FIR梯形滤波器对应的波束方向图。该16元波束形成器采用可重构开放架构计算硬件版本2 (ROACH-2)现场可编程门阵列(FPGA)平台实现,用于模拟数字转换和数字信号处理。2-D FIR梯形滤波器设计为16空间输入32分接滤波器,并针对ROACH-2的Xilinx Virtex 6 (sx475t) FPGA芯片实现滤波器和架构。接收器阵列精确旋转(保持发射器固定),通过积分二维FIR梯形滤波器输出的每个接收角度的瞬时功率来数字测量接收能量。测量到的波束方向图的主瓣与模拟波束方向图很好地对准,测量到的最高副瓣电平为−17.8 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Real-Time 2-D FIR Trapezoidal Digital Filters for 2.4 GHz Aperture Receiver Applications
This paper presents the implementation of a two-dimensional (2-D) finite-impulse-response (FIR) trapezoidal filter based beamforming array receiver. A 2.4 GHz 16-element receive-mode IQ array is designed and used for physically measuring the beam patterns corresponding to 2-D FIR trapezoidal filters. The 16-element beamformer is implemented using the reconfigurable open architecture computing hardware version-2 (ROACH-2) field programmable gate array (FPGA) platform to perform analog to digital conversion and digital signal processing. The 2-D FIR trapezoidal filter is designed as a 16-spatial input 32-tap filter and is implemented targeting the ROACH-2’s Xilinx Virtex 6 (sx475t) FPGA chip as a filter-and-sum architecture. The receiver array is precisely rotated (keeping the transmitter fixed) to digitally measure the received energy by integrating the instantaneous power of the output of the 2-D FIR trapezoidal filter for each angle of reception. The main lobe of the measured beam pattern is well aligned with the simulated beam pattern, and the highest measured side-lobe level is −17.8 dB.
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