A 4-bit CMOS full adder of 1-bit hybrid 13T adder with a new SUM circuit

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 4-bit FA using complementary metal oxide semiconductor (CMOS) technology had been designed successfully. A 1-bit hybrid FA (HFA) using 13 transistors (13T) with a new SUM circuit is the basis for the building block of the 4-bits FA. Four HFAs are cascaded together and each HFA is constructed from three modules. Exclusive-OR (XOR) gate of three transistors is the first module. The second one is the new SUM circuit designed using only four transistors to generate the HFA sum. The third module is a special carry circuit with input coming from the first module and several other inputs to generate the HFA carry output. The full adder design is simulated using Tanner EDA version 16 using General Process Design Kit (GPDK) of 250 nm CMOS technology. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1.8V voltage supply, the average power consumption of the proposed HFA was found extremely very low which is 2.09 μW and a moderately low delay of 350 ps. As for the 4-bit FA, the average power consumption is 65.37 μW with a delay of 1300 ps.