朝着低于1 V的CMOS电压基准

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI:10.1109/ISCAS.2004.1328129

L. Najafizadeh, I. Filanovsky

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引用次数: 28

摘要

提出了一种亚1伏的CMOS基准电压，该基准电压利用两个工作在饱和区的NMOS晶体管的栅极源电压之和。两个晶体管都工作在零下温度系数点，因此基准电压能够在低电源电压下工作。该电路在标准的0.18-/spl μ m CMOS工艺中实现，在-50/spl°C至150/spl°C范围内给出4 ppm//spl°C的温度系数。

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Towards a sub-1 V CMOS voltage reference

A sub-1-V CMOS voltage reference which takes advantage of summing the gate-source voltages of two NMOS transistors operating in saturation region is presented. Both transistors are working below zero temperature coefficient point and thus the voltage reference is able to operate with low supply voltage. The circuit is implemented in a standard 0.18-/spl mu/m CMOS process and gives a temperature coefficient of 4 ppm//spl deg/C in the range of -50/spl deg/C to 150/spl deg/C.

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来源期刊

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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