Y. Yokoyama, Nybutaka Itoh, Masap Katayama, K. Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, E. Yamasaki, Masaya Todokoro, Keinosuke Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka, N. Tamba
{"title":"1.8 v嵌入式18mb DRAM宏,RAS存取时间为9 ns,存储单元效率为33%","authors":"Y. Yokoyama, Nybutaka Itoh, Masap Katayama, K. Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, E. Yamasaki, Masaya Todokoro, Keinosuke Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka, N. Tamba","doi":"10.1109/CICC.2000.852666","DOIUrl":null,"url":null,"abstract":"A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"50 1","pages":"279-282"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%\",\"authors\":\"Y. Yokoyama, Nybutaka Itoh, Masap Katayama, K. Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, E. Yamasaki, Masaya Todokoro, Keinosuke Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka, N. Tamba\",\"doi\":\"10.1109/CICC.2000.852666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"50 1\",\"pages\":\"279-282\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%
A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.