1.8 v嵌入式18mb DRAM宏，RAS存取时间为9 ns，存储单元效率为33%

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852666

Y. Yokoyama, Nybutaka Itoh, Masap Katayama, K. Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, E. Yamasaki, Masaya Todokoro, Keinosuke Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka, N. Tamba

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引用次数: 2

摘要

开发了一种1.8 v嵌入式18mb DRAM，通过单面接口架构实现了33%的存储单元效率。实现了9 ns的RAS访问时间和4.6 ns的CAS访问时间，实现了40 Gb/s的数据转换速率。为了获得快速的访问时间，采用了多字冗余方案和YS合并感测方案。在VDD为1.8 V的情况下，通过引入抑制噪声电容，可将感应噪声降低至100 mV。

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A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%

A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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