{"title":"高关断增益高击穿电压n型SiC栅极关断晶闸管的设计与优化","authors":"Hongming Ma, Yan Wang","doi":"10.1109/ICICDT51558.2021.9626399","DOIUrl":null,"url":null,"abstract":"A N-type silicon carbide (SiC) gate turn-off thyristor (GTO) is designed and simulated with Sentaurus TCAD software, the detailed optimization process and final parameters are presented in this paper. By introducing 3-step JTE structure, a maximum breakdown voltage (BV) exceeding 15kV is achieved with 90μm drift layer, and over 13kV BV is available with an etching depth window of 0.28μm. By optimizing the P-base concentration, the maximum turn-off gain of the final structure is 6.01, and the forward voltage drop is 3.51V at 200A/cm2. The results show that this design can effectively increase the operating voltage and current of the power system while reducing dynamic loss.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and Optimization of N-type SiC Gate Turn-off Thyristor with High Turn-off Gain and High Breakdown Voltage\",\"authors\":\"Hongming Ma, Yan Wang\",\"doi\":\"10.1109/ICICDT51558.2021.9626399\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A N-type silicon carbide (SiC) gate turn-off thyristor (GTO) is designed and simulated with Sentaurus TCAD software, the detailed optimization process and final parameters are presented in this paper. By introducing 3-step JTE structure, a maximum breakdown voltage (BV) exceeding 15kV is achieved with 90μm drift layer, and over 13kV BV is available with an etching depth window of 0.28μm. By optimizing the P-base concentration, the maximum turn-off gain of the final structure is 6.01, and the forward voltage drop is 3.51V at 200A/cm2. The results show that this design can effectively increase the operating voltage and current of the power system while reducing dynamic loss.\",\"PeriodicalId\":6737,\"journal\":{\"name\":\"2021 International Conference on IC Design and Technology (ICICDT)\",\"volume\":\"35 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 International Conference on IC Design and Technology (ICICDT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT51558.2021.9626399\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on IC Design and Technology (ICICDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT51558.2021.9626399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Optimization of N-type SiC Gate Turn-off Thyristor with High Turn-off Gain and High Breakdown Voltage
A N-type silicon carbide (SiC) gate turn-off thyristor (GTO) is designed and simulated with Sentaurus TCAD software, the detailed optimization process and final parameters are presented in this paper. By introducing 3-step JTE structure, a maximum breakdown voltage (BV) exceeding 15kV is achieved with 90μm drift layer, and over 13kV BV is available with an etching depth window of 0.28μm. By optimizing the P-base concentration, the maximum turn-off gain of the final structure is 6.01, and the forward voltage drop is 3.51V at 200A/cm2. The results show that this design can effectively increase the operating voltage and current of the power system while reducing dynamic loss.
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