使用GDI逻辑的1位全加法器的性能分析

International Conference on Information Communication and Embedded Systems (ICICES2014) Pub Date : 2014-02-01 DOI:10.1109/ICICES.2014.7034029

S. Mohan, N. Rangaswamy

{"title":"使用GDI逻辑的1位全加法器的性能分析","authors":"S. Mohan, N. Rangaswamy","doi":"10.1109/ICICES.2014.7034029","DOIUrl":null,"url":null,"abstract":"This paper focuses on the design of 1 bit full adder circuit using Gate Diffusion Input Logic. The proposed adder schematics are developed using DSCH2 CAD tool, and their layouts are generated with Microwind 3 VLSI CAD tool. A 1 bit adder circuits are analyzed using standard CMOS 120nm features with corresponding voltage of 1.2V. The Simulated results of the proposed adder is compared with those of Pass transistor, Transmission Function, and CMOS based adder circuits. The proposed adder dissipates low power and responds faster.","PeriodicalId":13713,"journal":{"name":"International Conference on Information Communication and Embedded Systems (ICICES2014)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2014-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Performance analysis of 1 bit full adder using GDI logic\",\"authors\":\"S. Mohan, N. Rangaswamy\",\"doi\":\"10.1109/ICICES.2014.7034029\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper focuses on the design of 1 bit full adder circuit using Gate Diffusion Input Logic. The proposed adder schematics are developed using DSCH2 CAD tool, and their layouts are generated with Microwind 3 VLSI CAD tool. A 1 bit adder circuits are analyzed using standard CMOS 120nm features with corresponding voltage of 1.2V. The Simulated results of the proposed adder is compared with those of Pass transistor, Transmission Function, and CMOS based adder circuits. The proposed adder dissipates low power and responds faster.\",\"PeriodicalId\":13713,\"journal\":{\"name\":\"International Conference on Information Communication and Embedded Systems (ICICES2014)\",\"volume\":\"8 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Information Communication and Embedded Systems (ICICES2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICES.2014.7034029\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Information Communication and Embedded Systems (ICICES2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICES.2014.7034029","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

本文重点研究了采用门扩散输入逻辑的1位全加法器电路的设计。利用DSCH2 CAD工具编制了加法器原理图，并利用Microwind 3 VLSI CAD工具生成了加法器版图图。采用标准CMOS 120nm特性和1.2V电压对1位加法器电路进行了分析。将该加法器的仿真结果与通管、传输函数和CMOS加法器电路的仿真结果进行了比较。该加法器功耗低，响应速度快。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Performance analysis of 1 bit full adder using GDI logic

This paper focuses on the design of 1 bit full adder circuit using Gate Diffusion Input Logic. The proposed adder schematics are developed using DSCH2 CAD tool, and their layouts are generated with Microwind 3 VLSI CAD tool. A 1 bit adder circuits are analyzed using standard CMOS 120nm features with corresponding voltage of 1.2V. The Simulated results of the proposed adder is compared with those of Pass transistor, Transmission Function, and CMOS based adder circuits. The proposed adder dissipates low power and responds faster.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

International Conference on Information Communication and Embedded Systems (ICICES2014)

自引率

0.00%

发文量