阶梯掺杂高k VDMOS:开关特性

Shaivya Shukla, Onika Parmar, Amit Singh Rajput, Zeesha Mishra
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引用次数: 0

摘要

本文对垂直阶跃掺高k VDMOS的开关特性进行了分析。在HK VDMOS的n柱中引入垂直阶跃掺杂,提高了开关性能。所有的分析都是用银离子ATLAS工具进行的。不同的k值显著降低了切换延迟,k = 20时为40%,k = 10时为28.57%,k = 5时为31.76%。因此,当需要快速开关时,所提出的阶跃掺杂高k VDMOS可以取代高k VDMOS。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Stepped Doped High k VDMOS: Switching Characteristics
This paper presents the switching analysis of vertical stepped doped high k VDMOS. The introduction of vertical step doping in the n pillar of HK VDMOS brings improvement in switching performance. All the analysis of proposed and conventional device is carried out using silvaco ATLAS tool. Significant reduction in the switching delay is noted for different values of k. It is observed to be 40% for k = 20, 28.57% for k = 10, and 31.76% for k = 5. So the proposed step doped high k VDMOS can replace the high k VDMOS when fast switching is desired.
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