使用容错技术的缓存电压缩放限制

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI:10.1109/ICCD.2007.4601943

Avesta Sasan, A. Djahromi, A. Eltawil, F. Kurdahi

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引用次数: 25

摘要

本文提出了一种新的低功耗缓存架构，该架构利用容错能力来大幅降低电压水平。容错架空电路耗能小，但能使系统正常运行，提高系统性能，接近无缺陷运行。总体而言，在标准基准测试中报告的节电超过40%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Limits on voltage scaling for caches utilizing fault tolerant techniques

This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on standard benchmarks.

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2007 25th International Conference on Computer Design

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