嵌入式DRAM:一个元件和电路的评估

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852669

P. Diodato, J. O'Neill, Y. Wong, G. Alers, H. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C. Liu, W. Lai

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引用次数: 3

摘要

采用先进电容介质(Ta/sub 2/O/sub 5/)的嵌入式DRAM存储单元已被设计、制造和测量。存储单元数据保留时间用于比较四个Ta/sub 2/O/sub 5/设备供应商之间的电容器特性。一种类型的DRAM单元的静态性能归因于Ta/sub 2/O/sub 5/的双峰电流-电压特性和电路地形。

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Embedded DRAM: an element and circuit evaluation

Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta/sub 2/O/sub 5/, and circuit topography.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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