流水线adc中开环剩余放大器的数字辅助增益校准策略

S. Kazeminia, A. Soltani
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引用次数: 2

摘要

提出了一种开环残留放大器(RAs)的数字辅助类前景增益校准机制。同时使用两个相同的ra,依次对绝对增益值进行校正。虽然主RA与数据路径断开进行校准,但它被一个校正后的RA所取代,解决了常规前景方法中的不连续转换问题。数字辅助接口,包括inc/dec ACC和DAC,用于存储环路结果,即使RA离开校正环路。在所有角点条件下进行100次迭代的蒙特卡罗分析表明,校正回路的理想增益为4,中值为3.996,标准差为0.003,而阈值电压和参考电平在高斯分布的3σ处发生25mvolt的变化。线性,下降到9位50毫伏峰对峰变化的残留物。采用0.18μm CMOS技术的BSIM3v3模型进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs
A digitally-assisted foreground-liked gain calibration mechanism is proposed for open loop residue amplifiers (RAs). Two identical RAs are concurrently used which are in turn corrected for absolute gain value. Although the main RA is disconnected from data path for calibration, however, is replaced by a corrected one and resolves discontinuous conversion in regular foreground methods. A digitally assisted interface, includes inc/dec ACC and DAC, is utilized to store the loop results, even if RA leaves the correction loop. Monte-Carlo analysis for 100 iterations at all corner conditions shows that the correction loop provides ideal gain of 4 with median value of 3.996 and standard deviation of 0.003, while threshold voltages and reference levels experience 25mVolts variations at 3σ in Gaussian distribution. Linearity, drops to 9-bit for 50mVolts peak-to-peak variations on residue. Simulations are performed using the BSIM3v3 model of a 0.18μm CMOS technology.
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