{"title":"离散系统的最坏情况分析","authors":"F. Balarin","doi":"10.1109/ICCAD.1999.810673","DOIUrl":null,"url":null,"abstract":"We propose a methodology for worst-case analysis of systems with discrete observable signals. The methodology can be used to verify different properties of systems such as power consumption, timing performance or resource utilization. We also propose an application of the methodology to timing analysis of embedded systems implemented on a single processor. The analysis provides a bound on the response time of such systems. It is typically very efficient, because it does not require a state space search.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Worst-case analysis of discrete systems\",\"authors\":\"F. Balarin\",\"doi\":\"10.1109/ICCAD.1999.810673\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a methodology for worst-case analysis of systems with discrete observable signals. The methodology can be used to verify different properties of systems such as power consumption, timing performance or resource utilization. We also propose an application of the methodology to timing analysis of embedded systems implemented on a single processor. The analysis provides a bound on the response time of such systems. It is typically very efficient, because it does not require a state space search.\",\"PeriodicalId\":6414,\"journal\":{\"name\":\"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1999.810673\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1999.810673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We propose a methodology for worst-case analysis of systems with discrete observable signals. The methodology can be used to verify different properties of systems such as power consumption, timing performance or resource utilization. We also propose an application of the methodology to timing analysis of embedded systems implemented on a single processor. The analysis provides a bound on the response time of such systems. It is typically very efficient, because it does not require a state space search.