Non-uniform sampling based ADC architecture using an adaptive level-crossing technique

This paper presents a non-uniform sampling analog-to-digital converter (ADC) architecture using an adaptive level-crossing technique. The architecture can be dynamically configured through three parameters that allow the user to match the ADC to the signal to be acquired or to application constraints. When applied to sparse signals, this architecture outperforms uniform sampling architectures. In the case of an Electrocardiogram (ECG) signal, our architecture showed gains of up to 10 dB of signal to noise ratio (SNR) when considering the same number of samples of uniform sampling. When the same SNR is considered, our architecture allows reductions in excess of 50%. The architecture was implemented with FPGA and general purpose components, and showed a response time of about 200 μs, which could be further reduced in an integrated implementation.