M. Morsin, M. S. Sulong, Abdul Majeed bin Zulkipli, Tasiransurini Ab Rahman
{"title":"基于自旋掺杂技术的室内n阱MOSFET掩模设计、制造与表征","authors":"M. Morsin, M. S. Sulong, Abdul Majeed bin Zulkipli, Tasiransurini Ab Rahman","doi":"10.1109/ISIEA.2009.5356421","DOIUrl":null,"url":null,"abstract":"This paper presents a new innovative way of teaching undergraduate program using low cost masks to fabricate n-well MOSFET. The fabrication process of n-well MOSFET started with the establishment of process flow, process modules, and process parameters. The MOSFET fabrication process used blanket-field oxide for isolation, positive resist for lithography process, boron and phosphorus for source/drain doping and aluminum for metallization. An economical solution of masks using transparency films with various channel lengths from 300 µm to 500 µm has been produced to reduce cost. Six layer photolithography masks of MOSFET were designed using AutoCAD drawing tools and then printed using high resolution laser printer on the transparency film. Contact printing method has been utilized to transfer the mask layouts onto a 4-inch silicon wafer using standard photolithography techniques to check the line uniformity. Optical observation using high power microscope shows that the mask layouts were successfully transferred onto photoresist with minimum variation. The n-well CMOS transistors were tested using Keithley 2400 source meter with Lab-view measurement software. The obtained electrical characteristic is same as the theory.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"13 1","pages":"485-489"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Mask design, fabrication and characterization of in - house n-well MOSFET using spin -on dopant technique for undergraduates program\",\"authors\":\"M. Morsin, M. S. Sulong, Abdul Majeed bin Zulkipli, Tasiransurini Ab Rahman\",\"doi\":\"10.1109/ISIEA.2009.5356421\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new innovative way of teaching undergraduate program using low cost masks to fabricate n-well MOSFET. The fabrication process of n-well MOSFET started with the establishment of process flow, process modules, and process parameters. The MOSFET fabrication process used blanket-field oxide for isolation, positive resist for lithography process, boron and phosphorus for source/drain doping and aluminum for metallization. An economical solution of masks using transparency films with various channel lengths from 300 µm to 500 µm has been produced to reduce cost. Six layer photolithography masks of MOSFET were designed using AutoCAD drawing tools and then printed using high resolution laser printer on the transparency film. Contact printing method has been utilized to transfer the mask layouts onto a 4-inch silicon wafer using standard photolithography techniques to check the line uniformity. Optical observation using high power microscope shows that the mask layouts were successfully transferred onto photoresist with minimum variation. The n-well CMOS transistors were tested using Keithley 2400 source meter with Lab-view measurement software. The obtained electrical characteristic is same as the theory.\",\"PeriodicalId\":6447,\"journal\":{\"name\":\"2009 IEEE Symposium on Industrial Electronics & Applications\",\"volume\":\"13 1\",\"pages\":\"485-489\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Symposium on Industrial Electronics & Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISIEA.2009.5356421\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Symposium on Industrial Electronics & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISIEA.2009.5356421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Mask design, fabrication and characterization of in - house n-well MOSFET using spin -on dopant technique for undergraduates program
This paper presents a new innovative way of teaching undergraduate program using low cost masks to fabricate n-well MOSFET. The fabrication process of n-well MOSFET started with the establishment of process flow, process modules, and process parameters. The MOSFET fabrication process used blanket-field oxide for isolation, positive resist for lithography process, boron and phosphorus for source/drain doping and aluminum for metallization. An economical solution of masks using transparency films with various channel lengths from 300 µm to 500 µm has been produced to reduce cost. Six layer photolithography masks of MOSFET were designed using AutoCAD drawing tools and then printed using high resolution laser printer on the transparency film. Contact printing method has been utilized to transfer the mask layouts onto a 4-inch silicon wafer using standard photolithography techniques to check the line uniformity. Optical observation using high power microscope shows that the mask layouts were successfully transferred onto photoresist with minimum variation. The n-well CMOS transistors were tested using Keithley 2400 source meter with Lab-view measurement software. The obtained electrical characteristic is same as the theory.