Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications

Due to the end of Dennard scaling and Moore’s law, heterogeneous System-on-Chip (SoC) architectures are replacing complex hyper-pipelined processors to achieve high performance and energy efficiency. Such architectures feature many specialized components that can be used to accelerate selected computational kernels by exploiting more intrinsic parallelism with custom logic. Among them, FPGA devices are becoming common targets for these systems, since they allow fast turnaround time, field upgradability, and easy deployment of hardware/software solutions. However, co-designing FPGA systems still requires a combination of hardware and software design skills that are uncommon in most of the designers. To overcome these issues, designers need to raise the abstraction level from low-level manual designs to high-level approaches. High-level synthesis (HLS) is becoming a key enabling technology, especially for FPGA designs, since it allows designers to describe the functionality of a component at the software level and automatically generate the corresponding hardware description, enabling fast deployment of hardware/software solutions. HLS has been making tremendous progress in many application domains, ranging from Internet of Things and edge computing to data centers and cloud computing. While HLS is becoming more popular, the other side of the coin is that it is pushing the application landscape for hardware acceleration towards unprecedented challenges. On one hand, modern applications must elaborate huge amounts of data, demanding efficient methods for managing memory accesses. On the other hand, HLS is a complex process that produces itself a huge amount of information that can be used to drive further optimizations. In both cases, machine learning is coming to the rescue to extract valuable knowledge and make accurate predictions. In this special section, we have six articles covering both challenges (the first five articles) and application aspects (the last one). These articles show that HLS is a powerful but yet difficult-touse solution. Indeed, many HLS tools offer directives, i.e., source code annotations that trigger specific optimizations, but understanding the optimal combination from a huge design space is still a manual and time-consuming effort. The articles in this special section provide interesting insights on how to automate this exploration process also with the help of machine learning. We hope you will enjoy them and find them as interesting as we did. The special section opens with an article on the compiler-level optimizations for optimizing the pointer synthesis within HLS. “A case for precise, fine-grained pointer synthesis in high-level synthesis,” by N. Ramanathan et al., aims at reducing the gap between application designers, who could make heavy use of pointers to create compact and efficient software descriptions, and hardware designers, which demand precise memory information to implement the corresponding accesses