一种具有多层高压开关和选择性刷新方案的逻辑兼容嵌入式快闪存储器

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243824

Seung-hwan Song, K. Chun, C. Kim

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引用次数: 12

摘要

在具有5nm隧道氧化物的低功耗标准逻辑工艺中，演示了一种逻辑兼容的嵌入式闪存，该闪存除了使用标准核心和IO晶体管外，不使用任何特殊器件。无超压高压开关将单元VTH窗口扩展了> 170%，而5T嵌入式闪存单元采用了选择性行刷新方案，以提高耐用性。

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A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme

A logic-compatible embedded flash memory that uses no special devices other than standard core and IO transistors is demonstrated in a low-power standard logic process having a 5nm tunnel oxide. An overstress-free high voltage switch expands the cell VTH window by >;170% while a 5T embedded flash memory cell with a selective row refresh scheme is employed for improved endurance.

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2012 Symposium on VLSI Circuits (VLSIC)

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