Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Y. Kawamoto, Kenta Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, M. Yoshimoto
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A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.
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