用于GSM的高线性低功耗10位DAC

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852662

P. Ferguson, X. Haurie, G. Temes

{"title":"用于GSM的高线性低功耗10位DAC","authors":"P. Ferguson, X. Haurie, G. Temes","doi":"10.1109/CICC.2000.852662","DOIUrl":null,"url":null,"abstract":"A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is described. It features a low power quasipassive architecture with segmentation and element mismatch-shaping used in the conversion of the four MSBs. The DAC charge is entered into an integrated switched-capacitor biquad filter with passive charge sharing in the output stage, which passes the signal to a continuous time output stage. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at the 10-bit level with no calibration or trimming.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"45 1","pages":"261-264"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A highly linear low-power 10 bit DAC for GSM\",\"authors\":\"P. Ferguson, X. Haurie, G. Temes\",\"doi\":\"10.1109/CICC.2000.852662\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is described. It features a low power quasipassive architecture with segmentation and element mismatch-shaping used in the conversion of the four MSBs. The DAC charge is entered into an integrated switched-capacitor biquad filter with passive charge sharing in the output stage, which passes the signal to a continuous time output stage. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at the 10-bit level with no calibration or trimming.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"45 1\",\"pages\":\"261-264\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852662\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

介绍了一种用于GSM基带传输信道的10位6.5 MS/s DAC。它具有低功耗准无源架构，在四个msb的转换中使用了分段和元件错匹配整形。DAC电荷进入一个集成的开关电容双组滤波器，在输出级无源电荷共享，将信号传递到连续时间输出级。DAC在10位水平上实现小于1/4位DNL和0.6位INL，无需校准或微调。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A highly linear low-power 10 bit DAC for GSM

A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is described. It features a low power quasipassive architecture with segmentation and element mismatch-shaping used in the conversion of the four MSBs. The DAC charge is entered into an integrated switched-capacitor biquad filter with passive charge sharing in the output stage, which passes the signal to a continuous time output stage. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at the 10-bit level with no calibration or trimming.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

自引率

0.00%

发文量