SMiTe:基于实时系统SMT处理器的精确QoS预测,以提高仓库规模计算机的利用率

Yunqi Zhang, M. Laurenzano, Jason Mars, Lingjia Tang
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引用次数: 128

摘要

提高仓库规模计算机(WSCs)效率的关键挑战之一是在保证对延迟敏感的应用程序的服务质量(QoS)的同时提高服务器利用率。为此,先前的工作已经提出了精确预测性能和QoS干扰的技术,以确定“安全”的应用程序共存。然而,这些技术只适用于跨核心共享的资源。由于内核内资源共享带来的复杂性,在实系统同步多线程(SMT)架构上实现如此精确的干扰预测一直是一个极具挑战性的开放性问题。在本文中,我们通过实际系统调查证明,CMP和SMT架构上资源共享行为之间的根本差异要求我们重新设计建模干扰的方式。对于SMT服务器,对不同共享资源(包括私有缓存、内存端口以及整数和浮点功能单元)的干扰彼此不相关。这一见解表明了将干扰解耦到多个资源共享维度的必要性。在这项工作中,我们提出了SMiTe,这是一种能够在实际系统商品处理器上精确预测SMT协同定位性能的方法。通过一组标尺,这些标尺是精心设计的软件压力源,对共享资源的多维空间施加压力,我们以解耦的方式量化应用程序的敏感性和争议性。然后,我们建立了一个回归模型,结合不同维度的敏感性和争议性来预测性能干扰。使用该方法,我们能够准确地预测SMT共置中的性能干扰,在SPEC CPU2006上的平均误差为2.80%,在Cloud Suite上的平均误差为1.79%。我们的评估表明,SMiTe允许我们在执行应用程序的QoS需求的同时,将wsc的利用率提高42.57%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers
One of the key challenges for improving efficiency in warehouse scale computers (WSCs) is to improve server utilization while guaranteeing the quality of service (QoS) of latency-sensitive applications. To this end, prior work has proposed techniques to precisely predict performance and QoS interference to identify 'safe' application co-locations. However, such techniques are only applicable to resources shared across cores. Achieving such precise interference prediction on real-system simultaneous multithreading (SMT) architectures has been a significantly challenging open problem due to the complexity introduced by sharing resources within a core. In this paper, we demonstrate through a real-system investigation that the fundamental difference between resource sharing behaviors on CMP and SMT architectures calls for a redesign of the way we model interference. For SMT servers, the interference on different shared resources, including private caches, memory ports, as well as integer and floating-point functional units, do not correlate with each other. This insight suggests the necessity of decoupling interference into multiple resource sharing dimensions. In this work, we propose SMiTe, a methodology that enables precise performance prediction for SMT co-location on real-system commodity processors. With a set of Rulers, which are carefully designed software stressors that apply pressure to a multidimensional space of shared resources, we quantify application sensitivity and contentiousness in a decoupled manner. We then establish a regression model to combine the sensitivity and contentiousness in different dimensions to predict performance interference. Using this methodology, we are able to precisely predict the performance interference in SMT co-location with an average error of 2.80% on SPEC CPU2006 and 1.79% on Cloud Suite. Our evaluation shows that SMiTe allows us to improve the utilization of WSCs by up to 42.57% while enforcing an application's QoS requirements.
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