{"title":"STM-64的再生段开销处理芯片组","authors":"Seog-Hoon Lee, Jong-ho Kim, Donghoon Kim","doi":"10.1109/APCAS.1996.569250","DOIUrl":null,"url":null,"abstract":"A chip set has been designed for the 10 Gb/s SDH-based optical transmission system and developed using GaAs gate array technology. The features supported by the chip set include 8:1 multiplexing and demultiplexing, frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, and B1 byte insertion and error detection. This paper describes the architecture, implementation, and experimental results of the chip set, and parallel circuit design technologies suitable for the very high-speed SDH-based optical transmission system.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"11 1","pages":"187-190"},"PeriodicalIF":0.0000,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A regenerator section overhead processing chip set for STM-64\",\"authors\":\"Seog-Hoon Lee, Jong-ho Kim, Donghoon Kim\",\"doi\":\"10.1109/APCAS.1996.569250\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A chip set has been designed for the 10 Gb/s SDH-based optical transmission system and developed using GaAs gate array technology. The features supported by the chip set include 8:1 multiplexing and demultiplexing, frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, and B1 byte insertion and error detection. This paper describes the architecture, implementation, and experimental results of the chip set, and parallel circuit design technologies suitable for the very high-speed SDH-based optical transmission system.\",\"PeriodicalId\":20507,\"journal\":{\"name\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"volume\":\"11 1\",\"pages\":\"187-190\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCAS.1996.569250\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCAS.1996.569250","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A regenerator section overhead processing chip set for STM-64
A chip set has been designed for the 10 Gb/s SDH-based optical transmission system and developed using GaAs gate array technology. The features supported by the chip set include 8:1 multiplexing and demultiplexing, frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, and B1 byte insertion and error detection. This paper describes the architecture, implementation, and experimental results of the chip set, and parallel circuit design technologies suitable for the very high-speed SDH-based optical transmission system.
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