木材- v:标签隔离内存带来细粒度飞地RISC-V

Samuel Weiser, M. Werner, Ferdinand Brasser, Maja Malenko, S. Mangard, A. Sadeghi
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引用次数: 72

摘要

嵌入式计算设备在新兴的物联网(IoT)中得到了大规模的应用。然而,正如最近的几次攻击所证明的那样,它们的广泛部署增加了攻击者瞄准这些设备的动机。由于物联网设备的使用寿命较长,因此需要在存在潜在漏洞的情况下保护敏感代码,这些漏洞可能在部署后很长时间才被发现。标记内存被提议作为一种在运行时执行各种细粒度安全策略的机制。然而,就孤立的执行环境而言,现有的标记内存方案都没有提供有效和灵活的分区。我们提出了TIMBER-V,一种新的标记内存架构,在小型嵌入式系统上灵活有效地隔离代码和数据。我们克服了以前方案的几个限制。我们使用内存保护单元增强标签隔离,以隔离单个进程,同时保持低内存开销。TIMBER-V显著减少了内存碎片问题,并改进了跨安全边界的不可信内存的动态重用。除了交错堆之外,TIMBER-V还支持跨不同安全域共享执行堆栈。TIMBER-V与现有代码兼容,支持实时约束,并且是开源的。我们通过在RISC-V模拟器上评估我们的概念验证实现来展示TIMBER-V的效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V
Embedded computing devices are used on a large scale in the emerging internet of things (IoT). However, their wide deployment raises the incentive for attackers to target these devices, as demonstrated by several recent attacks. As IoT devices are built for long service life, means are required to protect sensitive code in the presence of potential vulnerabilities, which might be discovered long after deployment. Tagged memory has been proposed as a mechanism to enforce various fine-grained security policies at runtime. However, none of the existing tagged memory schemes provides efficient and flexible compartmentalization in terms of isolated execution environments. We present TIMBER-V, a new tagged memory architecture featuring flexible and efficient isolation of code and data on small embedded systems. We overcome several limitations of previous schemes. We augment tag isolation with a memory protection unit to isolate individual processes, while maintaining low memory overhead. TIMBER-V significantly reduces the problem of memory fragmentation, and improves dynamic reuse of untrusted memory across security boundaries. TIMBER-V enables novel sharing of execution stacks across different security domains, in addition to interleaved heaps. TIMBER-V is compatible to existing code, supports real-time constraints and is open source. We show the efficiency of TIMBER-V by evaluating our proofof-concept implementation on the RISC-V simulator.
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