Acceleration of Software Transactional Memory through Hardware Clock

Transactional Memory (TM) has gained momentum mainly due to its ability to provide synchronization transparency in parallel programs. In transactional applications, accesses to the shared data structures are handles by TM layer with no intervention by a programmer. Time-based software transactional memories (STMs) exploit a global clock to validate transactional data. Unfortunately, the clock becomes a bottleneck especially in programs with large number of concurrent transactions. In this paper, we exploit hardware support to implement the global clock. The hardware clock is implemented on the processor chip and enables bottleneck-free transactional memory run-time systems. Our evaluation using Gem5 simulator shows that the hardware clock is effective and reduces execution time of Stamp benchmarks up to 62%.