{"title":"三维电网建模","authors":"Larissa Zlydina, Y. Yagil","doi":"10.1109/ICECS.2004.1399631","DOIUrl":null,"url":null,"abstract":"The paper describes on-chip 3D power grid (PG) modeling for high performance CPU designs. We show that for high frequencies (above 1 GHz) it is necessary to use the full RLM PG model with extracted partial self and mutual conductors' inductances, rather than resistive R or RL models. We also present a practical model reduction technique named \"real space reduction\" (RSR), which enables simplifying the model and reduces memory and simulation time without significant accuracy losses.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"3D power grid modeling\",\"authors\":\"Larissa Zlydina, Y. Yagil\",\"doi\":\"10.1109/ICECS.2004.1399631\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes on-chip 3D power grid (PG) modeling for high performance CPU designs. We show that for high frequencies (above 1 GHz) it is necessary to use the full RLM PG model with extracted partial self and mutual conductors' inductances, rather than resistive R or RL models. We also present a practical model reduction technique named \\\"real space reduction\\\" (RSR), which enables simplifying the model and reduces memory and simulation time without significant accuracy losses.\",\"PeriodicalId\":38467,\"journal\":{\"name\":\"Giornale di Storia Costituzionale\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Giornale di Storia Costituzionale\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2004.1399631\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Giornale di Storia Costituzionale","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2004.1399631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Arts and Humanities","Score":null,"Total":0}
The paper describes on-chip 3D power grid (PG) modeling for high performance CPU designs. We show that for high frequencies (above 1 GHz) it is necessary to use the full RLM PG model with extracted partial self and mutual conductors' inductances, rather than resistive R or RL models. We also present a practical model reduction technique named "real space reduction" (RSR), which enables simplifying the model and reduces memory and simulation time without significant accuracy losses.
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