基于SRF-PLL的正序列同步相量测量算法的设计与测试

Gabriel Ubirajara de Carvalho, Gustavo Weber Denardin, R. Cardoso, C. F. Moraes
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引用次数: 0

摘要

本文介绍了一种基于SRF-PLL的正序同步量测量算法的设计、分析和实验测试,该算法符合IEEE C37.118.1-2011和c37.118.1 -2014标准。该方法由三阶段算法组成,第一阶段是三相解调,在频域将正序列与负序列信号分离,并去除零序列。第二阶段是有限脉冲响应滤波器(FIR),用于提高噪声和抗干扰性。这类数字滤波器是根据其线性相位和恒定群延迟的特性来选择的。最后,采用幅度归一化的同步参考帧锁相环和比例积分控制器进行最后一步,估计振幅、相位、频率和频率变化率。在实验平台上进行的实验结果表明,该方法满足稳态准则。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and Test of a SRF-PLL Based Algorithm for Positive-Sequence Synchrophasor Measurements
This paper presents the design, analysis and experimental testing of a SRF-PLL based algorithm for positive-sequence synchrophasor measurements in compliance with the IEEE C37.118.1-2011 and C37.118.1a-2014 standards. The proposed approach consists of a three-stage algorithm, being the first one a three-phase demodulation, which detach the positive-sequence from the negative sequence signal in the frequency domain, as well as removes the zero sequence. The second stage is a finite impulse response filter (FIR) that is applied in order to improve the noise and interference rejection. Such class of digital filters was chosen by its characteristics of linear phase and constant group delay. Finally, the last stage is carried out by a synchronous reference frame phase-locked loop featuring magnitude normalization and proportional-integral controller, which estimates amplitude, phase, frequency and rate of change of frequency. The experimental results obtained by a test platform show that steady-state criteria are met.
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