多克隆行DRAM:低延迟、区域优化的DRAM

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA) Pub Date : 2015-06-13 DOI:10.1145/2749469.2750402

Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, L. Kim

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引用次数: 49

摘要

以前的一些工作已经改变了DRAM存储结构，以减少内存访问延迟，并显示出性能改进。但是，对区域优化的DRAM库进行更改可能会导致较大的区域开销。为了解决这个问题，我们提出了多克隆行DRAM (MCR-DRAM)，它使用现有的DRAM库结构而不做任何修改。

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Multiple Clone Row DRAM: A low latency and area optimized DRAM

Several previous works have changed DRAM bank structure to reduce memory access latency and have shown performance improvement. However, changes in the area-optimized DRAM bank can incur large area-overhead. To solve this problem, we propose Multiple Clone Row DRAM (MCR-DRAM), which uses existing DRAM bank structure without any modification.

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2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA)

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