UART IP核的设计与仿真分析

2011 Second International Conference on Mechanic Automation and Control Engineering Pub Date : 2011-07-15 DOI:10.1109/MACE.2011.5988319

Shihua Tong

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引用次数: 1

摘要

在掌握SOPC和Quartus II的基础上，设计了UART IP核，并给出了完整的设计方案。该方案嵌入在FPGA芯片中。对发射模块、接收模块和波特率发生器进行了仿真和分析。实验结果表明，该设计方法紧凑实用，电路稳定可靠，灵活性强。

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Design and simulation analysis of UART IP Core

Based on mastering SOPC and Quartus II, designed UART IP Core, and an integrity design proposal is given out. The proposal is embedded in FPGA chip. The transmitter module, receiver module and baud rate generator are simulated and analyses. The experiments results show that the design method is compact and practical, and the circuit is stable, reliable, and strong flexibility.

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来源期刊

2011 Second International Conference on Mechanic Automation and Control Engineering

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