3D-IC缺陷容限的增强双tsv方案

Hsiu-Chuan Shih, Cheng-Wen Wu
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引用次数: 0

摘要

基于硅通孔(TSV)的芯片堆叠被认为是一种有效的降低功耗和外形尺寸的方法。现阶段,TSV的故障率仍然很高,因此需要某种缺陷容限方案。同时,传统层对层互连中常用的双通孔概念也可以作为一种可行的容差方案。与TSV维修相比,双通孔/TSV有一个好处:它可以省去保险丝的配置程序以及保险丝层。然而,双tsv存在短缺陷引起的信号退化和泄漏问题。本文提出了一种改进的双tsv方案,通过信号路径分割和VDD隔离来解决短缺陷问题。结果表明,改进后的双tsv既能容忍开路缺陷,又能容忍短路缺陷,且具有合理的面积和时序开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An enhanced double-TSV scheme for defect tolerance in 3D-IC
Die stacking based on Through-Silicon Via (TSV) is considered as an efficient way to reducing power consumption and form factor. In the current stage, the failure rate of TSV is still high, so some type of defect tolerance scheme is required. Meanwhile, the concept of double-via, which is normally used in traditional layer to layer interconnection, can be one of the feasible tolerance schemes. Double-via/TSV has a benefit compared to TSV repair: it can eliminate the fuse configuration procedure as well as the fuse layer. However, double-TSV has a problem of signal degradation and leakage caused by short defects. In this work, an enhanced scheme for double-TSV is proposed to solve the short-defect problem through signal path division and VDD isolation. Result shows that the enhanced double-TSV can tolerate both open and short defects, with reasonable area and timing overhead.
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