镀边铜柱C2W焊的研究

Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno
{"title":"镀边铜柱C2W焊的研究","authors":"Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno","doi":"10.1109/ECTC.2017.260","DOIUrl":null,"url":null,"abstract":"Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1572-1577"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Study of C2W Bonding Using Cu Pillar with Side-Wall Plated Solder\",\"authors\":\"Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno\",\"doi\":\"10.1109/ECTC.2017.260\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.\",\"PeriodicalId\":6557,\"journal\":{\"name\":\"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"1 1\",\"pages\":\"1572-1577\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2017.260\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2017.260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

Cu-Cu是互连的首选,因为与Cu-Solder bump相比,它提供了更低的电阻,没有碰撞之间的短路风险和更高的可靠性。然而,Cu-Cu互连对铜碰撞表面形貌、平整度、柱阵高度均匀性和连接表面清洁等条件提出了严格的要求。从通量的角度来看,Cu-Cu键合是具有挑战性的,因为键合曲线涉及长加热时间和高温。在本文中,我们探索了提高键合吞吐量和改善互连形成的方法。提出了一种新型铜柱结构,其核心铜柱被侧壁层焊料包围。该铜柱阵列通过芯片到晶圆(C2W)方法键合在带有铜衬垫的底部晶圆上。研究表明,位于侧壁的焊料有助于将芯片暂时固定在晶圆上。然后整个互连通过使用团伙粘合形成连接。由于侧壁焊料将单个铜柱密封到相应的键合垫上,有助于防止柱阵中的非接触互连或空隙互连。采用粘接和粘接工艺,可以实现更高的吞吐量,并因其装配成本较低而被工业积极采用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Study of C2W Bonding Using Cu Pillar with Side-Wall Plated Solder
Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.
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