{"title":"一种用于10gbit /s sdh光纤传输系统的全断面架空处理芯片组","authors":"T. Lee, J. Cho, Jeong-Hoon Ko","doi":"10.1109/ICICS.1997.652161","DOIUrl":null,"url":null,"abstract":"A full section overhead (SOH) processing chip set has been designed for use in a 10 Gbit/s SDH-based optical fiber transmission system. The chip set has been fabricated in a 0.6 /spl mu/m CMOS and GaAs gate array technology. The features supported by the chip set include STM-64 SOH insertion and extraction including regenerator section trace (RST), frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, 8:1 multiplexing and demultiplexing, alarm detection and generation, and performance monitoring. This paper introduces a novel multiplexing and demultiplexing structure for a parallel processing of the STM-64 signal using the chip set. This paper also describes the architecture of the chip set, and several of the chip set's more interesting features.","PeriodicalId":71361,"journal":{"name":"信息通信技术","volume":"16 1","pages":"1143-1147 vol.2"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ICICS.1997.652161","citationCount":"1","resultStr":"{\"title\":\"A full section overhead processing chip set for 10 Gbit/s SDH-based optical fiber transmission system\",\"authors\":\"T. Lee, J. Cho, Jeong-Hoon Ko\",\"doi\":\"10.1109/ICICS.1997.652161\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A full section overhead (SOH) processing chip set has been designed for use in a 10 Gbit/s SDH-based optical fiber transmission system. The chip set has been fabricated in a 0.6 /spl mu/m CMOS and GaAs gate array technology. The features supported by the chip set include STM-64 SOH insertion and extraction including regenerator section trace (RST), frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, 8:1 multiplexing and demultiplexing, alarm detection and generation, and performance monitoring. This paper introduces a novel multiplexing and demultiplexing structure for a parallel processing of the STM-64 signal using the chip set. This paper also describes the architecture of the chip set, and several of the chip set's more interesting features.\",\"PeriodicalId\":71361,\"journal\":{\"name\":\"信息通信技术\",\"volume\":\"16 1\",\"pages\":\"1143-1147 vol.2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1109/ICICS.1997.652161\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"信息通信技术\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICS.1997.652161\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"信息通信技术","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ICICS.1997.652161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
设计了一种用于10gbit /s sdh光纤传输系统的全分段开销(SOH)处理芯片组。该芯片组采用0.6 /spl μ m CMOS和GaAs门阵列技术制造。芯片组支持的功能包括STM-64 SOH插入和提取(包括再生段跟踪(RST))、帧对齐字插入和检测、32位并行置乱和解扰、8:1多路复用和解路复用、报警检测和生成以及性能监控。本文介绍了一种利用该芯片组并行处理STM-64信号的复用解复用结构。本文还介绍了该芯片组的结构,以及该芯片组的几个比较有趣的特性。
A full section overhead processing chip set for 10 Gbit/s SDH-based optical fiber transmission system
A full section overhead (SOH) processing chip set has been designed for use in a 10 Gbit/s SDH-based optical fiber transmission system. The chip set has been fabricated in a 0.6 /spl mu/m CMOS and GaAs gate array technology. The features supported by the chip set include STM-64 SOH insertion and extraction including regenerator section trace (RST), frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, 8:1 multiplexing and demultiplexing, alarm detection and generation, and performance monitoring. This paper introduces a novel multiplexing and demultiplexing structure for a parallel processing of the STM-64 signal using the chip set. This paper also describes the architecture of the chip set, and several of the chip set's more interesting features.