{"title":"基于Markov聚类的分层FPGA布局算法","authors":"Dai Hui (戴晖), Zhou Qiang (周强), Bian Jinian (边计年)","doi":"10.1016/S1007-0214(11)70010-4","DOIUrl":null,"url":null,"abstract":"<div><p>Divide-and-conquer methods for FPGA<span><span> placement algorithms including partition-based and cluster-based algorithms have shown the importance of good quality-runtime trade-off. This paper describes a cluster-based FPGA placement algorithm targeted to a new commercial hierarchical FPGA device. The algorithm is based on a Markov clustering algorithm that defines a sequence of stochastic matrices operating on a generating matrix from the input FPGA circuit netlist. The core of the algorithm tightly couples a Markov clustering process with a multilevel placement process. Tests show its excellent adaptability to hierarchical FPGAs. The average wirelength results produced by the algorithm are 22.3% shorter than the results produced by the current hierarchical FPGA </span>placer.</span></p></div>","PeriodicalId":60306,"journal":{"name":"Tsinghua Science and Technology","volume":null,"pages":null},"PeriodicalIF":5.2000,"publicationDate":"2011-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S1007-0214(11)70010-4","citationCount":"2","resultStr":"{\"title\":\"Markov Clustering-Based Placement Algorithm for Hierarchical FPGAs*\",\"authors\":\"Dai Hui (戴晖), Zhou Qiang (周强), Bian Jinian (边计年)\",\"doi\":\"10.1016/S1007-0214(11)70010-4\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Divide-and-conquer methods for FPGA<span><span> placement algorithms including partition-based and cluster-based algorithms have shown the importance of good quality-runtime trade-off. This paper describes a cluster-based FPGA placement algorithm targeted to a new commercial hierarchical FPGA device. The algorithm is based on a Markov clustering algorithm that defines a sequence of stochastic matrices operating on a generating matrix from the input FPGA circuit netlist. The core of the algorithm tightly couples a Markov clustering process with a multilevel placement process. Tests show its excellent adaptability to hierarchical FPGAs. The average wirelength results produced by the algorithm are 22.3% shorter than the results produced by the current hierarchical FPGA </span>placer.</span></p></div>\",\"PeriodicalId\":60306,\"journal\":{\"name\":\"Tsinghua Science and Technology\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":5.2000,\"publicationDate\":\"2011-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/S1007-0214(11)70010-4\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Tsinghua Science and Technology\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1007021411700104\",\"RegionNum\":1,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"COMPUTER SCIENCE, INFORMATION SYSTEMS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Tsinghua Science and Technology","FirstCategoryId":"1093","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1007021411700104","RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, INFORMATION SYSTEMS","Score":null,"Total":0}
Markov Clustering-Based Placement Algorithm for Hierarchical FPGAs*
Divide-and-conquer methods for FPGA placement algorithms including partition-based and cluster-based algorithms have shown the importance of good quality-runtime trade-off. This paper describes a cluster-based FPGA placement algorithm targeted to a new commercial hierarchical FPGA device. The algorithm is based on a Markov clustering algorithm that defines a sequence of stochastic matrices operating on a generating matrix from the input FPGA circuit netlist. The core of the algorithm tightly couples a Markov clustering process with a multilevel placement process. Tests show its excellent adaptability to hierarchical FPGAs. The average wirelength results produced by the algorithm are 22.3% shorter than the results produced by the current hierarchical FPGA placer.