Performance Analysis of Charge-plasma Based Doping less Nanowire Field Effect Transistor

The proposed work focuses on the outcomes brought about by the inclusion of Charge Plasma (CP) concept in a cylindrical Nanowire Field Effect Transistor (NWFET) for sub 10 nm. The Gate is surrounded by an oxide layer, which is further surrounded by a channel layer. The concept of charge-plasma is introduced in the channel by surrounding an oxide layer around the channel, and a different work functions metal layer around the oxide. The performance of device parameters like the electric potential and transfer characteristics have been described. Analysis of Threshold Voltage, drain current and I ON / I OFF ratio have been carried for 35 nm and 10 nm channel length. Sentaurus Technology Computer Aided Design (TCAD) has been used to evaluate and analyze this device for sub 10 nm. To calculate tunneling and recombination, the TCAD simulates the Lombardi mobility model, Shockley-Read-Hall (SRH), Density Gradient model, and Auger recombination models. This device generates twice times more output current by using the CP-based NWFET as compared to the conventional NWFET. The parasitic leakage has been reduced and the I ON /I OFF ratio has been stabilized. Also, the scalability is enhanced, and the Schottky junction's high vertical field lowers the lateral coupling between the source and drain field lines. This can be used to implement in memory devices such as Inverter, 6T SRAM