基于3-T异或门的低功耗高效进位选择加法器设计

Q3 Engineering

Advances in Optoelectronics Pub Date : 2014-09-22 DOI:10.1155/2014/564613

Gagandeep Singh, C. Goel

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引用次数: 3

摘要

在数字系统中，加法器大多位于影响系统整体性能的关键路径上。为了实现低成本的快速加法运算，进位选择加法器(CSLA)是传统加法器结构中最适合的。本文采用3-T异或门设计8位CSLA，因为异或门是设计更高位加法器的基本模块。与常规CSLA和改进的CSLA相比，拟议的CSLA减少了晶体管数量，功耗和功率延迟产品(PDP)也更低。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.

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来源期刊

Advances in Optoelectronics ENGINEERING, ELECTRICAL & ELECTRONIC-

CiteScore

1.30

自引率

0.00%

发文量

期刊介绍： Advances in OptoElectronics is a peer-reviewed, open access journal that publishes original research articles as well as review articles in all areas of optoelectronics.