A single-event-hardened phase-locked loop using the radiation-hardened-by-design technique

A radiation-hardened-by-design phase-locked loop (PLL) with a frequency range of 200 to 1000 MHz is proposed. By presenting a novel charge compensation circuit, composed by a lock detector circuit, two operational amplifiers, and four MOS devices, the proposed PLL significantly reduces the recovery time after the presence of a single event transient (SET). Comparing with many traditional hardened methods, most of which endeavor to enhance the immunity of the charge pump output node to an SET, the novel PLL can also decrease its susceptibility in the presence of an SET in other blocks. A novel system model is presented to describe immunity of a PLL to an SET and used to compare the sensitivity of traditional and hardened PLLs to an SET. An SET is simulated on Sentaurus TCAD simulation workbench to model the induced pulse current. Post simulation with a 130 nm CMOS process model shows that the recovery time of the proposed PLL reduces by up to 93.5% compared with the traditional one, at the same time, the charge compensation circuit adds no complexity to the systemic parameter design.