C. Buttay;T.B. Salah;D. Bergogne;B. Allard;H. Morel;J.-P. Chante
{"title":"低压功率MOSFET的雪崩行为","authors":"C. Buttay;T.B. Salah;D. Bergogne;B. Allard;H. Morel;J.-P. Chante","doi":"10.1109/LPEL.2004.839638","DOIUrl":null,"url":null,"abstract":"This letter addresses the behavior of low voltage power MOSFETs under avalanche, with a paralleling point of view. It is shown that during avalanche, up-to-date technology MOSFET transistors exhibit a resistance far in excess of their on-state resistance (R/sub DSon/). A novel test setup is proposed to measure \"avalanche\" resistance. A simple model of breakdown voltage is then proposed. It becomes possible to perform fast simulations using this model to study current balance between paralleled transistors under avalanche operation. It is shown that considering avalanche resistance reduces the influence of breakdown voltage mismatches and allows for better current sharing.","PeriodicalId":100635,"journal":{"name":"IEEE Power Electronics Letters","volume":"2 3","pages":"104-107"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/LPEL.2004.839638","citationCount":"21","resultStr":"{\"title\":\"Avalanche behavior of low-voltage power MOSFETs\",\"authors\":\"C. Buttay;T.B. Salah;D. Bergogne;B. Allard;H. Morel;J.-P. Chante\",\"doi\":\"10.1109/LPEL.2004.839638\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter addresses the behavior of low voltage power MOSFETs under avalanche, with a paralleling point of view. It is shown that during avalanche, up-to-date technology MOSFET transistors exhibit a resistance far in excess of their on-state resistance (R/sub DSon/). A novel test setup is proposed to measure \\\"avalanche\\\" resistance. A simple model of breakdown voltage is then proposed. It becomes possible to perform fast simulations using this model to study current balance between paralleled transistors under avalanche operation. It is shown that considering avalanche resistance reduces the influence of breakdown voltage mismatches and allows for better current sharing.\",\"PeriodicalId\":100635,\"journal\":{\"name\":\"IEEE Power Electronics Letters\",\"volume\":\"2 3\",\"pages\":\"104-107\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1109/LPEL.2004.839638\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Power Electronics Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/1359817/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Power Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/1359817/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This letter addresses the behavior of low voltage power MOSFETs under avalanche, with a paralleling point of view. It is shown that during avalanche, up-to-date technology MOSFET transistors exhibit a resistance far in excess of their on-state resistance (R/sub DSon/). A novel test setup is proposed to measure "avalanche" resistance. A simple model of breakdown voltage is then proposed. It becomes possible to perform fast simulations using this model to study current balance between paralleled transistors under avalanche operation. It is shown that considering avalanche resistance reduces the influence of breakdown voltage mismatches and allows for better current sharing.
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