Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm

Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer’s views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today’s tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx’s early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.