超低功耗2比1复用器设计的动态功耗和延迟分析

IF 0.5 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Advances in Electrical and Electronic Engineering Pub Date : 2021-06-30 DOI:10.15598/AEEE.V19I2.3821

Nishant Kumar, P. Mittal, B. Rawat, Mudit Mittal

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引用次数: 3

摘要

本文重点对2到1多路复用器实现的八种不同技术进行了比较分析。功能是相同的，但在动态功耗和传播延迟方面观察到显著差异。本文旨在使设计者能够根据他们的设计要求，为特定应用选择最合适的结构。多路复用器是在90nm技术节点上设计的，并在1V的电源电压下进行模拟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Dynamic Power Consumption and Delay Analysis for Ultra-Low Power 2 to 1 Multiplexer Designs

This paper highlights a comparative analysis of eight diverse techniques for 2 to 1 multiplexer implementation. The functionality is identical but significant differences in dynamic power consumption and propagation delay are observed. This paper aims to enable the designer to pick out the best fit structure for a specific application in keeping with their design requirement. The multiplexers are designed at 90 nm technology node and simulated at a supply voltage of 1V.

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来源期刊

Advances in Electrical and Electronic Engineering ENGINEERING, ELECTRICAL & ELECTRONIC-

CiteScore

1.30

自引率

33.30%

发文量

审稿时长

25 weeks