Yong‐Yun Park, Won‐Ho Jang, Kyoung-Ho Kim, K. Ryu, Jung-Pil Lim, Y. Kwon, H. Lim, Jae-Youl Lee
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23‐3: Distinguished Paper: A Clock Embedded Intra‐panel Interface with 1.96% Data Overhead for Beyond 8K Displays
This paper proposes a 6Gb/s receiver for 8K displays and beyond. In the proposed receiver, a novel channel coding with 1.96% overhead is presented to guarantee minimum run‐length in the clock embedded interface. It can also reduce bandwidth for effective data transmission compared to 9b/10b coding that requires 11.11% overhead. Furthermore, we present an on‐chip eye margin tester that can measure the internal timing margin of receiver with only 1% area overhead. The prototype ICs are implemented using 0.18‐μm HVCMOS process and evaluated in an 8K 65‐inch panel.
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