FPGA Implementation of Secure Internet of Things (SIT) Algorithm for High Throughput Area Ratio

In this paper, we present the results of hardware implementation of our previously proposed lightweight encryption algorithm named as Secure Internet of Things (SIT). By virtue of its low cost and computational simplicity, SIT can be a good candidate to meet the needs of resource constraint applications related to the futuristic demands of Internet of Things. In this work, we have implemented our proposed SIT algorithm on Field Programmable Gate Array (FPGA) and compared the results with the similar implementations reported in the literature. During the hardware implementation, we focused on obtaining high throughput area ratio which is essential parameter for the applications focusing on internet of things. Our implementation of the SIT algorithm on FPGA achieved a throughput of 4899 Mbps with encryption while using only 711 logic elements resulting in throughput area ratio of 6.89.