低功耗高可靠性SET诱导的双节点翻转硬化锁存器和触发器

IF 1.7 Q2 Engineering

Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique Pub Date : 2019-06-24 DOI:10.1109/CJECE.2019.2895047

Riadul Islam

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引用次数: 4

摘要

从一代工艺技术到下一代工艺工艺技术，对摩尔定律的不懈追求似乎增加了电路对单事件瞬态（SET）引起的双节点扰乱（SEDU）的脆弱性。在本文中，我们提出了一种新型的SEDU硬化闩锁。锁存器由一个新的16晶体管（16T）SEDU硬化存储单元和一个C型输出缓冲器组成。与现有的SEDU硬化锁存器相比，该锁存器的功耗降低了25%，速度加快了81%，并且功率延迟乘积也降低了86%。此外，我们还提出了第一个具有负保持时间的SEDU硬化触发器。所提出的SEDU硬化触发器比现有的部分SEDU硬化的触发器快29%，消耗50%的动态功率和25%的静态功率，具有45%的设置时间，并且使用27%的面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low-Power Highly Reliable SET-Induced Dual-Node Upset-Hardened Latch and Flip-Flop

It appears that the relentless pursuit of Moore’s law scaling from one generation of process technology to the next increases circuit vulnerability to single-event transient (SET)-induced double-node upset (SEDU). In this paper, we present a novel SEDU-hardened latch. The latch consists of a new 16-transistor (16T) SEDU-hardened storage cell and a C-type output buffer. The latch exhibits 25% lower power consumption, is 81% faster, and also shows 86% lower power-delay product than the existing SEDU-hardened latches. In addition, we present the first SEDU-hardened flip-flop that exhibits negative hold time. The proposed SEDU-hardened flip-flop is 29% faster, consumes 50% lower dynamic power and 25% lower static power, has 45% lower setup time, and uses 27% lower area than the existing partial SEDU-hardened flip-flop.

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来源期刊

Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique 工程技术-工程：电子与电气

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0.00%

发文量

期刊介绍： The Canadian Journal of Electrical and Computer Engineering (ISSN-0840-8688), issued quarterly, has been publishing high-quality refereed scientific papers in all areas of electrical and computer engineering since 1976