{"title":"具有轨对轨运行能力的低功率高增益放大器:在生物医学信号处理中的应用","authors":"H. F. Baghtash, Rasoul Pakdel","doi":"10.53560/ppasa(58-1)684","DOIUrl":null,"url":null,"abstract":"low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.","PeriodicalId":36961,"journal":{"name":"Proceedings of the Pakistan Academy of Sciences: Part A","volume":" ","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing\",\"authors\":\"H. F. Baghtash, Rasoul Pakdel\",\"doi\":\"10.53560/ppasa(58-1)684\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.\",\"PeriodicalId\":36961,\"journal\":{\"name\":\"Proceedings of the Pakistan Academy of Sciences: Part A\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Pakistan Academy of Sciences: Part A\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.53560/ppasa(58-1)684\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Physics and Astronomy\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Pakistan Academy of Sciences: Part A","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.53560/ppasa(58-1)684","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Physics and Astronomy","Score":null,"Total":0}
A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing
low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.