A Novel Approach to Reduce the Crosstalk in Graphene Based Interconnects Using Ternary Logic

This paper presents a novel approach to reduce the impact of crosstalk in multi-layered GNR (MLGNR), single walled CNT (SWCNT), multiwalled CNT (MWCNT) and mixed CNT bundle (MCB) based three-line bus architecture system. The proposed system primarily comprises of active shielding, repeater insertion and asymmetric triggering of the input signal. At the far end of the bus architecture, the crosstalk induced noise and propagation delay of MLGNR, SWCNT, MWCNT and MCB interconnects have been analyzed with and without the impact of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at the output. Using the specified output, a temperature dependent comparative analysis is also performed for MLGNR and bundled CNT interconnects with and without shielding. Using industry standard HSPICE circuit simulations, it can be observed that the MLGNR offers a lower paracitic values even in higher temperature in comparison to the SWCNT, MWCNT and MCB interconnects. It primarily leads to a lesser delay and crosstalk using a bus interconnect system. The analysis has also extended for delay and crosstalk analysis for different interconnect lengths and temperatures with an insertion of shielding, repeaters and asymmetric triggering of bus architecture system. Under these conditions, it is also proved that an MLGNR based bus architecture offers a lesser crosstalk induced delay and noise compared to CNT bundle interconnects.