Reconfigurable hardware architecture of public key crypto processor for VANET and wireless sensor nodes

This work proposes encryption of text and image data, embedding as elliptic curve point. Finite field arithmetic is utilised efficiently in this reconfigurable crypto system. Pre-computations for text data and image input conversion is done using MATLAB. This architecture is tailored for cryptographic applications and VANET using Xilinx Spartan-xc3s100e-4-fg320 FPGA with Verilog coding. Total encryption and decryption time results around 10.09021 microseconds for 100×100 images, 22.091 microseconds for 256×256 images and 0.029 microseconds for a message. The message size is varied with different stream size and dynamic mapping of input data and a cipher image with high randomness indicates good security i.e., less vulnerable to attacks. An entropy statistical analysis is performed on plain and encrypted images to assess the strength of the proposed method. An encryption throughput rate is 450 Mbps and area throughput 3.63, which is a good improvement over previous implementations.