Power Oriented Optimization for the Defect-Tolerant Mapping of CMOL Circuits

Aiming at the power consumption increase problem from the defects of CMOS/nanowire/ molecular hybrid (CMOL) circuits, a defect-tolerant mapping method based on cell limitation is proposed. First, the power consumption model of defect pairs is established and the effect of different mapping patterns of the defect pairs on power consumption is analyzed. Then, the use of power hungry cells is restricted and the power consumption constraint is set to reduce the power consumption overhead caused by the high cost mapping patterns. Finally, the modified genetic algorithm is chosen to implement the defect-tolerant mapping of CMOL circuits. The ISCAS benchmarks are tested for verification. The experimental results demonstrated that the proposed method effectively reduces the power consumption and area of CMOL circuits on the basis of successful defect-tolerance, with better optimization of solution speed.