高掺杂硅衬底上低温等离子体外延硅的电学特性

IF 1.9 Q3 PHYSICS, APPLIED
C. Léon, S. Le Gall, M. Gueunier‐Farret, J. Kleider, P. Roca i Cabarrocas
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引用次数: 0

摘要

使用等离子体增强化学气相沉积工艺(PECVD)在低温下在高掺杂的c-Si衬底上生长外延硅层(175 °C)。通过电流密度-电压(J–V)和电容-电压(C–V)技术表征了这些外延硅层的传输和缺陷相关特性。结果表明,外延硅层表现出非故意的n型掺杂,其表观掺杂密度约为2 × 1015厘米-3。导纳谱技术用于研究结构中深层缺陷的存在。0.2的能级 已发现导带下方的eV密度在1015 cm−3范围内,这可以解释观察到的表观掺杂分布。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Electrical characterization of low temperature plasma epitaxial Si grown on highly doped Si substrates
Epitaxial silicon layers were grown on highly doped c-Si substrates using the plasma-enhanced chemical vapour deposition process (PECVD) at low temperature (175 °C). The transport and defect-related properties of these epi-Si layers were characterized by current density-voltage (J–V) and capacitance–voltage (C–V) techniques. The results show that the epi-Si layers exhibit a non-intentional n-type doping with a low apparent doping density of about 2 × 1015 cm−3. The admittance spectroscopy technique is used to investigate the presence of deep-level defects in the structure. An energy level at 0.2 eV below the conduction band has been found with a density in the range of 1015 cm−3 which may explain the observed apparent doping profile.
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来源期刊
EPJ Photovoltaics
EPJ Photovoltaics PHYSICS, APPLIED-
CiteScore
2.30
自引率
4.00%
发文量
15
审稿时长
8 weeks
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