Improving on current using new double-material heterojunction gate all around TFET (DMHJGAA TFET): Modeling and simulation

Transistor, which is the building block of all electronic devices, has continuously scaled down its dimensions for better efficiency since the advent of CMOS circuits. Due to the thermal limit on the switching and various short-channel effects (SCEs), highly scaled MOSFETs are rendered unusable for low-power applications. Hence, the Tunnel Field-Effect Transistors (TFETs) are studied extensively for ultra-low-power applications. Further, multigate TFETs have emerged as the prime candidates for achieving better gate controllability. Throughout this work, a newly revised analytical model for Heterojunction Gate All Around (HJGAA) TFET is demonstrated using a 2D parabolic approximation equation. Analytical expressions are derived for both potential distribution and field distribution using appropriate boundary conditions. This distribution of electric fields is further used to measure the rate of tunneling output, and then we have extracted the drain current numerically. The findings indicate a substantial change in the drain current characteristics while reducing the SCE impacts to a considerable amount. Feasibility of the newly updated model is verified by comparing the results of the analytical model with the results of TCAD simulator.