{"title":"23.4 mW−72 dBc参考杂散40 GHz CMOS PLL,具有杂散补偿相位检测器","authors":"Yuan Liang, C. Boon, Qian Chen","doi":"10.1109/LMWC.2022.3153326","DOIUrl":null,"url":null,"abstract":"This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- $N$ phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1091-1094"},"PeriodicalIF":2.9000,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 23.4 mW −72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector\",\"authors\":\"Yuan Liang, C. Boon, Qian Chen\",\"doi\":\"10.1109/LMWC.2022.3153326\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- $N$ phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.\",\"PeriodicalId\":13130,\"journal\":{\"name\":\"IEEE Microwave and Wireless Components Letters\",\"volume\":\"32 1\",\"pages\":\"1091-1094\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2022-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Microwave and Wireless Components Letters\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1109/LMWC.2022.3153326\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Microwave and Wireless Components Letters","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1109/LMWC.2022.3153326","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 23.4 mW −72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector
This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- $N$ phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.
期刊介绍:
The IEEE Microwave and Wireless Components Letters (MWCL) publishes four-page papers (3 pages of text + up to 1 page of references) that focus on microwave theory, techniques and applications as they relate to components, devices, circuits, biological effects, and systems involving the generation, modulation, demodulation, control, transmission, and detection of microwave signals. This includes scientific, technical, medical and industrial activities. Microwave theory and techniques relates to electromagnetic waves in the frequency range of a few MHz and a THz; other spectral regions and wave types are included within the scope of the MWCL whenever basic microwave theory and techniques can yield useful results. Generally, this occurs in the theory of wave propagation in structures with dimensions comparable to a wavelength, and in the related techniques for analysis and design.