图像处理中并行处理的位平面切片芯片

IF 1.2 4区综合性期刊 Q3 MULTIDISCIPLINARY SCIENCES

National Academy Science Letters Pub Date : 2023-08-19 DOI:10.1007/s40009-023-01344-6

Adesh Kumar

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引用次数: 0

摘要

位平面分割（BPS）的目的是将原始图像分割成不同的位平面。首先将像素值转换成二进制形式，然后再分割成位平面。这封研究信的重点是实现 BPS 概念的硬件芯片，其中（8 × 8）图像被配置为 8 个平面。实现过程在 Xilinx ISE14.7 中进行并行处理，平面的功能验证在 Modelsim 10.0 中完成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

Bit Plane Slicing Chip Using Parallel Processing in Image Processing

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Bit Plane Slicing Chip Using Parallel Processing in Image Processing

The objective of bit plane slicing (BPS) is to split the original image into different bit planes. The pixel values are first transformed into binary form and then split into bit planes. The research letter focuses on the concept of realizing the hardware chip for the BPS concept in which (8 × 8) image is configured into 8 planes. The realization is followed using the parallel processing in Xilinx ISE14.7 and functional verification of the planes is done in Modelsim 10.0.

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来源期刊

National Academy Science Letters 综合性期刊-综合性期刊

CiteScore

2.20

自引率

0.00%

发文量

审稿时长

12 months

期刊介绍： The National Academy Science Letters is published by the National Academy of Sciences, India, since 1978. The publication of this unique journal was started with a view to give quick and wide publicity to the innovations in all fields of science